1. Field of the Invention
The present invention relates generally to a semiconductor memory circuit, and more particularly to a memory circuit with a redundant memory cell array ensuring simplified shipment tests and reduced power consumptions.
2. Description of the Related Arts
A static RAM, one of the semiconductor memory circuits, is incorporated as a high-speed memory in, e.g., the system LSI. The static RAM has a memory cell in which inputs and outputs of a pair of CMOS inverters are cross connected to each other. One of the pair of CMOS inverters outputs H level signal whilst the other outputs L level, such that data is latched so that no current is consumed in data holding state.
The recent static RAM must meet the stringent requirement for larger capacity, in addition to its quick access capability. With the increased capacity of the static RAM, a redundant memory cell array is generally disposed in order to relieve failed cells or failed bits.
A shipping tests of the static RAM include two types of tests, a function test for checking, after predetermined data is written, whether the same data is correctly read out, and a leak test for checking, after predetermined data is first written and then held for a predetermined time, whether the same data remains held correctly. The function test is a test for checking whether write-in and read-out can properly be performed as regular memory, and this test detects as faults a short-circuit between bit lines or a trouble in the memory cell. On the contrary, the leak test detects as a fault, if leak current flows in the data hold state and data cannot be held, because of a failed transistor of the memory cell. Leak from the bit line is also regarded as one of leak faults.
When any fault is detected by the function test or by the leak test of the static RAM, the cell array is replaced with a redundant cell array in order to relieve these faults. For example, Japanese Patent Application Laid-open (kokai) Pub. No. H08-138399 proposes providing a redundant replacement memory for replacing the cell array that has failed in the function test with a redundant cell array, and a redundant replacement memory for replacing the cell array that has failed in the leak test with a redundant cell array. In this prior art, the bit line pre-charge path to the cell array that has failed in the leak test is turned off, such that pre-charge to that cell array having any leak fault is prohibited so that power consumption is cut down. To turn this pre-charge path off, a redundant replacement memory for leak test is employed.
In the above prior art, the function test and the leak test are carried out separately, and the addresses of the cell arrays that have failed in these tests are stored in respective redundant replacement memories, resulting in a complicated circuit configuration.
Another problem may occur. When a fault is detected in a memory cell array, data on the cell array having a failed bit to be replaced with a redundant cell array is written in a redundant replacement memory in order to achieve the replacement with the redundant cell array, and after that the redundant cell array needs to be subjected to the function test and the leak test.
However the redundant replacement memory is typically comprised of a fuse ROM, and the step of writing to this fuse ROM takes a long period of time since the step involves fusing of the fuse element by laser beam, thus adding to costs for the testing.